Data buses are used in integrated circuits (ICs) to transfer data between master devices, such as user-controlled microprocessors, and slave devices controlling peripheral devices, such as memories and the like. One such bus design is an Advanced High-performance Bus (AHB) from ARM Limited of Cambridge, England. The AHB bus design is a form of an Advanced Microcontroller Bus Architecture (AMBA) bus. The AHB bus provides high performance, high clock frequency data transfer between multiple bus master devices and multiple bus slave devices through use of an arbiter. The AHB bus is particularly useful in integrated circuit chips, including single chip processors, to couple processors to on-chip memories and to off-chip external memory interfaces.
The AHB bus is a pipelined bus that operates in two phases, a command phase followed by a data transfer phase. The master device instructs, or commands, the slave device during the command phase to perform a specific type of data transaction, and the slave device transfers data with the master device during the data transfer phase. For example, a read command will command the slave to read data from its storage device and transfer that data to the master device via the data bus during the data transfer phase. A write command will command the slave to receive data from the master device during the data transfer phase for storage within the storage device. A typical AHB bus includes a 32-bit data bus to transfer up to four 8-bit bytes during a single beat. Other AHB bus configurations exist for buses capable of handling 1024 bits (128 bytes) during a single beat.
In the AHB bus, a write command is accompanied by an address in the peripheral device to which data are to be written, as well as a fixed-byte data transfer format, known as a Legacy format, that includes burst information (called HBURST) identifying the number of beats and burst type, and size information (called HSIZE) identifying the size (number of bytes) of the transfer. Master and slave devices operating on the Legacy format are known as Legacy devices. Each byte of data is written to a location in the storage device designated by an address. The addresses of successive bytes of data are calculated from an address of a first byte using the HBURST and HSIZE information. In the Legacy format, the size information is limited by the number of bits in the HSIZE code. The HSIZE data is 3 bits, representing eight combinations that define eight pre-defined sizes of transfer: 1, 2, 4, 8, 16, 32, 64 and 128 bytes to be transferred during the beats specified by the HBURST code.
As used herein, a “fixed-byte” format is a transfer format in which a prescribed number of bytes is transferred during a given transaction. Thus, the Legacy format is a “fixed-byte” format because each transaction is limited to transfer of one of the eight pre-defined number of bytes. The term “odd-byte” refers to a number of bytes that is not the same as a number of bytes prescribed by a pre-defined transfer size of the bus transfer format. Stated another way, an odd-byte format is any format that is not a fixed-byte format.
To transfer a group of data bytes that is not equal to the number of bytes prescribed by one of the eight pre-defined sizes of data transfer (i.e., an odd-byte transfer), the AHB bus is required to perform several independent transactions. For example, in the AHB bus it is not possible to perform a 3-byte transfer as a single transaction. Instead, a 3-byte transfer is performed by two transactions: a 2-byte transfer and a 1-byte transfer, or vice versa.
Data buses exist that permit transfer of various sized data bursts using byte-enabled formats, and master and slave devices are available for such buses to perform byte-enabled transfers. A byte-enabled transfer is accomplished with a byte-enable code associated with each beat of data transfer to identify the validity of each byte in the beat. For example, if a bus contains 32 data lines, carrying four 8-bit bytes, a 4-bit byte-enable code indicates which bytes are valid and which are invalid. Consequently, a 3-byte transfer can be accomplished simply by indicating which three bytes of the transfer are valid using the 4-bit byte-enable code. However, buses employing fixed-byte formats, such as the AHB bus, cannot accommodate byte-enable devices because these buses cannot handle odd-byte formats.
It is desirable to couple devices that operate in a byte-enable transfer format to a bus that operates in a fixed-byte data format. One attempt is found in the Lo et al. U.S. Pat. No. 6,366,973, where an interface circuit is provided for byte-enable slave devices to permit fixed-byte master devices to transfer data with the byte-enable slave device. Lo proposes an interface circuit that translates transfer codes associated with fixed-byte format transfers of an Advanced System Bus (ASB) to a PCI format, a form of byte-enable transfer, and to translate transfer codes associated with certain byte-enable transfers to the fixed-byte format. However, the Lo approach cannot translate odd-byte byte-enable transfer formats to the fixed-byte transfer. More particularly, the ASB bus operates in single word transfers of one, two and four bytes. The Lo interface circuit translates the ASB command to byte-enable by setting one, two or four bits of the byte-enable code to indicate valid bytes, and translates the byte-enable transfer code to ASB format by translating byte-enable codes that contain one validity bit, two consecutive validity bits and four validity bits to the corresponding ASB code. The Lo interface circuit cannot handle odd-byte transfers of three bytes or of two non-consecutive bytes.
The ASB bus is a single word transfer bus, and while it can transfer multiple word bursts, it does not employ burst descriptors as in the AHB bus that specifies the number of beats and burst type. Consequently, the Lo interface circuit will not successfully operate, in a bus environment where plural words are transferred in a single transaction, such as in the AHB bus.